1. Field of the Invention
This invention relates to packaging structures for integrated circuit chips and more particularly to control of functions thereof.
2. Description of Related Art
U.S. Pat. No. 5,789,303 of Leung et al., assigned to Northern Telecom Limited for xe2x80x9cMethod of Adding on Chip Capacitors to an Integrated Circuitxe2x80x9d shows thin capacitors (100) and (200) deposited on the planarized surface of chips in FIGS. 3 and 4. The capacitor layers are formed by deposition, photolithographic masking, etching, and selective deposition as described at Col. 5, lines 17-50.
U.S. Pat. No. 5,814,871 of Furukawa et al assigned to Fujitsu, Ltd. for xe2x80x9cOptical Semiconductor Assembly Having a Conductive Floating Padxe2x80x9d shows a chip capacitor (44) or (46) in FIG. 4C. thereof formed on the surface of a xe2x80x9cmetal stem 6xe2x80x9d which carries a preamplifier IC (28).
U.S. Pat. No. 5,926,061 of Kawasaki assigned to Fujitsu, for xe2x80x9cPower Supply Noise Eliminating Method and Semiconductor Devicexe2x80x9d shows what appears to be a planar on-chip capacitor C2 on chip (2) in FIG. 24 and described at Col. 10, lines 19-34.
U.S. Pat. No. 5,963,110 of Ihara et al., assigned to Fujitsu, for xe2x80x9cEqualizing Filter and Control Method for Signal Equalizationxe2x80x9d shows a chip capacitor C2T in FIG. 14 bridging a pair of output patterns (P1) and (P2) and described at Col. 7, lines 26-39.
U.S. Pat. No. 4,598,307 of Wakabayashi et al. for xe2x80x9cIntegrated Circuit Device Having Package with Bypass Capacitorxe2x80x9d shows a bypass capacitor mounted externally in an opening in a marginal area of the lid of a Integrated Circuit (IC) chip package, which is an Dual-In-Line (DIP) type package.
U.S. Pat. No. 5,475,262 of Wang et al. for xe2x80x9cFunctional Substrates for Packaging Semiconductor Chipsxe2x80x9d shows stacked multiple levels of interconnected substrates with a separate signal connection substrate, a separate capacitor substrate, a separate resistor substrate, and a separate power supply substrate. Confronting substrates have a plurality of bond pads which are interconnected by inter-substrate contacts between the substrates which may be deformable bumps or other electrical connectors or contacts selected from solder bumps, elastomer bumps and gold bumps.
U.S. Pat. No. 5,498,906 of Roane et al. for xe2x80x9cCapacitive Coupling Configuration for an Integrated Circuit Packagexe2x80x9d shows an externally mounted bypass capacitor for a IC package.
U.S. Pat. No. 5,608,262 of Degani et al. for xe2x80x9cPackaging Multi-Chip Modules without Wire-Bond Interconnectionxe2x80x9d describes at Col. 4, lines 8-11 xe2x80x9ca silicon-on-silicon structure having a silicon substrate . . . provided with metallizations to which each chip or die . . . is interconnected in a flip-chip manner by means of solder . . . .xe2x80x9d
U.S. Pat. No. 5,854,534 of Bilin et al. for xe2x80x9cControlled Impedance Interposer Substratexe2x80x9d shows an interposer which incorporates a bypass capacitor.
U.S. Pat. No. 5,898,223 of Frye et al. for xe2x80x9cChip-on-Chip Packagexe2x80x9d shows chip-on-chip packages using solder bump interchip connections as vias between a single level interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper chip using solder bumps to form connections between the confronting chips.
U.S. Pat. No. 5,939,782 of Malladi shows a xe2x80x9cPackage Construction for an Integrated Circuit Chip with a Bypass Capacitorxe2x80x9d buried in a compartment defining an inner chamber in a multilayer substrate formed of a number of generally parallel insulating layers.
U.S. Pat. No. 5,818,748 of Bertin and Cronin for xe2x80x9cChip Function Separation onto Separate Stacked Chipsxe2x80x9d shows an chips stacked face to face connected together both physically and electrically by FSC""s (Force responsive Self-interlocking microConnectors) including confronting pedestals on which FSC""s are formed.
U.S. Pat. No. 5,977,640 of Bertin et al for xe2x80x9cHighly Integrated Chip-on-Chip Packagingxe2x80x9d shows a chip-on-chip component connection/interconnection for electrically connecting functional chips to external circuitry.
Takahashi et al. xe2x80x9c3-Dimensional Memory Modulexe2x80x9d, Semi, pp. 166-167 (1997) shows a stack of flip chips on carriers processed starting with flip chip bonding to a carrier and followed by the steps of epoxy resin casting, polishing, bump formation for stacking, and stacking multiple carriers.
The invention teaches a methods of mounting discrete chips on a chip package or multi-chip package which may include a bypass capacitor.
An object of this invention is to provide flexibility of functions of multiple chip packages.
Another object of this invention is to provide a separate inventory of products with different functions.
Still another object of this invention is control circuit design in the single chip for example for function selection.
Another object of this invention is to pack a bypass capacitor in package or in combination chip package.
A problem solved by this invention is reduction of the inventory of several products with different functions.
Another object of this invention is to eliminate I/O noise.
A chip package for semiconductor chips is provided by the method of this invention.
In accordance with a first aspect of this invention a method of forming a chip package for a semiconductor chip include the following steps to provide a device in accordance with this invention. Form a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from (a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board. Form solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection. Preferably, provide a bypass capacitor with a first terminal and a second terminal, and connect the first terminal of the bypass capacitor to the power structure and connect the second terminal of the bypass capacitor to the ground structure. Juxtapose the capacitor and the power bus and the ground bus with the chip, and connect the first terminal to the power bus or power plane and connect the second terminal to the ground bus or ground plane. Alternatively, locate the capacitor on the opposite surface of the printed circuit board from the chip, and connect the first terminal to the power plane and connect the second terminal to the ground plane. Preferably, connect big solder balls to the opposite surface of the printed circuit board for interconnection thereof with another element.
In accordance with another aspect of this invention a method of forming a chip package for a semiconductor chip and the device produced thereby includes the following steps. Form a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board. Form a second printed circuit board having a top surface and a bottom surface. Bond a first chip to the top surface of the first printed circuit board and bond a second chip to the bottom surface of the first printed circuit board in a flip chip connection. Bond a third chip to the bottom surface of the second printed circuit board in a flip chip connection. Bond the chips to the printed circuit boards by means selected solder balls and gold bumps. Provide a bypass capacitor with a first terminal and a second terminal. Connect the first terminal of the bypass capacitor to the power plane. Connect the second terminal of the bypass capacitor to the ground plane. In an alternative feature, bond a fourth chip to the top surface of the second printed circuit board in a flip chip connection. Interconnect the bottom surface of the first printed circuit board and the top surface of the second printed circuit board with big solder balls. Preferably, bond a fourth chip to the second printed circuit board top surface. Provide a bypass capacitor with a first terminal and a second terminal. Connect the first terminal of the bypass capacitor to the power plane and connecting the second terminal of the bypass capacitor to the ground plane.
In accordance with still another aspect of this invention, a method of forming a chip package for semiconductor chips includes the following steps. Form a printed circuit board with a window therethrough having a length and a width and a top surface and a bottom surface. The Semiconductor chips include a primary chip and a secondary chip. Form bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window. Then locate the secondary chip suspended within the window and form bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection. Preferably, the window has a width less than the length; and the primary chip and the secondary chip have substantially equal chip lengths and substantially equal chip widths. Form the bonded connections of the chips to the printed circuit boards by means selected from solder balls and gold bumps. Preferably, form the bonded connections of the chips to the printed circuit board by means selected from a) solder balls, and b) gold bumps. Form big solder balls on the top surface of the printed circuit board.
In accordance with one more aspect of this invention, a method of forming a chip package for semiconductor chips includes the following steps. Provide a substrate having a top surface and a bottom surface. The semiconductor chips include a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface. Form bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and form bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving space between the secondary chip and the printed circuit board. The substrate comprises a ball grid array substrate. The bonded connections of the chips to the substrate are provided by means selected from solder balls, and gold bumps. Preferably, form the bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip with big solder balls, the substrate comprising a ball grid array substrate, and the bonded connections of the chips to the substrate being provided by means selected from a)solder balls, and b)gold bumps.
A method of interconnecting semiconductor chips includes steps and the device produced thereby are as follows. There are semiconductor chips including a primary chip and a secondary chip, the primary chip having a top surface and the secondary chip having a bottom surface. Form bonded chip-on-chip connections between the bottom surface of the secondary chip and the top surface of the primary chip. Form bonded connections between the top surface of the primary chip aside from the secondary chip. Preferably, there are bonded connections between the top surface of the primary chip aside from the secondary chip to Tape Automated Bonding (TAB) leads.
A method of forming a chip package for semiconductor chips and the device produced thereby includes the following steps. Form a printed circuit board with a top surface and a window therethrough. Connect two or more primary semiconductor chips each of which only partially overlies the window to the top surface of a printed circuit board by solder bonds. Connect a secondary semiconductor chip located within the window to at least of the two primary chips overlying the window in a chip-on-chip connection. Preferably, connect big solder balls to the top surface of the printed circuit board aside from the primary semiconductor chips.
Finally, another aspect of this invention includes forming a chip package for a semiconductor chip and the product produced thereby by the following steps. Form a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which include a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board. Form solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections. Provide a bypass capacitor with a first terminal and a second terminal. Connect the first terminal of the bypass capacitor to the power structure and connect the second terminal of the bypass capacitor to the ground structure. Form optional pads for connection to optional solder balls for functional selection.